Synchronous operation is provided by hav- ing all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output count- ing spikes normally associated with asynchronous ripple clock counters. A HIGH at the enable input inhibits counting. The counter is fully programmable; that is, the outputs may be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input.
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This banner text can have markup. Search the history of over billion web pages on the Internet. Synchronous operation is provided by having all flip- flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asyn- chronous ripple clock counters.
A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock in- put is high.
When low, the counter count up and when high, it counts down. These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows.
The ripple clock output produces a low-level output pulse equal in width to the low- level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used.
Production processing does not necessarily include testing of all parameters. Pin numbers shown are for D, J, and N packages. Load preset to BCD seven. Count up to eight, nine maximum , zero, one, and two. Count down to one, zero minimum , nine, eight, and seven. Lqad preset to binary thirteen.
Count up to fourteen, fifteen maximum , zero, one, and two. Count down to one, zero minimum , fifteen, fourteen, and thirteen. NOTES: 2. I qq is measured with all inputs grounded and all outputs open.
Minimum count enable time is the interval immediately preceeding the rising edge of the clock pulse during which interval the count enable input must be low to ensure counting. For simplication, pulse rise times, reference levels, etc. All diodes are 1 N or equivalent. Data input D is shown by the dashed line. Data inputs B and C are held at the low logic level.
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